|Name:||Mont-Blanc, European Approach towards Energy Efficient HPC|
|Time:||Tuesday, June 19, 2012
12:00 PM - 12:30 PM
CCH - Congress Center Hamburg
|Speakers:||Mateo Valero, Barcelona Supercomputing Center|
|Abstract:||It is widely recognized that Exascale systems will be constrained by power. The Mont-Blanc project aims to build an alternative approach towards Exascale based on aggregating parts from the embedded and mobile market, which offer a better FLOPS/Watt ratio and a lower unit cost, at the expense of lower peak performance per chip. HPC systems built from these parts will require a higher number of processors, or resort to extensive use of compute accelerators. Using a higher number of chips increases the available memory bandwidth, alleviating the bandwidth wall, but increases the pressure on the interconnection network.
The use of a high number of processors and accelerators, and the increased pressure on the interconnect require extensive code optimizations to achieve strong scaling, point to point synchronizations, and overlap data transfer with computation. The role of the OmpSs parallel programming model is paramount, as the key enabling technology that hides the complexity from the programmer, and transparently performs all the required optimizations.
In this talk, we will review the design philosophies of several vendors, including HPC compute accelerators, and ARM-based mobile application processors in terms of peak performance, memory bandwidth, and energy efficiency; and we will review how the OmpSs programming models exploits the benefits of the Mont-Blanc approach while overcoming the drawbacks.