|Name:||A Theory for Co-Designing Algorithms & Architectures under Power & Chip-Area Constraints|
|Time:||Tuesday, June 19, 2012
4:20 PM - 4:40 PM
CCH - Congress Center Hamburg
|Speakers:||Richard Vuduc, Georgia Institute of Technology|
|Abstract:||Given a computation, is there an time-optimal machine architecture that can meet desired power and chip-area (transistors) constraints? We describe a formal framework that marries abstract algorithmic complexity analysis with *physically-based* cost models for time, energy, power, and die area. These costs are the key limiting factors in the design of extreme scale systems for 2018 and beyond. Our ultimate goal is to say precisely and analytically how high-level changes to an architecture--with respect to cores, memory, and networks--might affect the execution time, scalability, accuracy, and power-efficiency of a computation; and, conversely, to identify what classes of computation might best match a given architecture.
This work is joint with Kent Czechowski, Casey Battaglino, Aparna Chandramowlishwaran, and Jee Choi, all of whom are PhD students at Georgia Tech.