|Name:||Accelerating Neural Network Computation Using Wafer-Scale Neuromorphic Hardware|
|Time:||Wednesday, June 20, 2012
2:45 PM - 3:15 PM
CCH - Congress Center Hamburg
|Speakers:||Johannes Schemmel, University of Heidelberg|
|Abstract:||Modeling neural tissue by directly emulating the electrical behavior of neurons and synapses in VLSI CMOS circuits - usually termed Neuromorphic Hardware - is at present time the only technologically feasible alternative to the numerical approach in neural network computation. Although it is around since the dawn of the digital age, it has not yet been able to make an impact on computational neuroscience.
This talk will present results from the European research project "BrainScales", which aims at building Neuromorphic Hardware systems targeted for neuroscience research. Therefore, they need to keep the resource efficiency of analog circuits while simultaneously using digital technologies to provide a sufficient level of configurability to support the needs of the modeling community.
In addition, since neuromorphic systems operate in continuous time without the time multiplexing of computing resources employed in Turing-based approaches, a large number of components has to be operated in parallel to be able to model networks of interesting size.
The presented solution is a mixed-signal approach emulating biological models in continuous time with an acceleration factor of typically 104 compared to the biological real-time. The system is built from uncut silicon wafers employing an additional wafer-scale metallization layer on top which provides a communication network interconnecting all dies of the wafer.
The resulting maximum computing power per wafer crosses the barrier of one Petaconnection/s.