June 17-21, 2012

Hamburg, Germany

Contribution Details

Name: Achieving Ultra-Low Latencies with Electrical Interconnects
Time: Wednesday, June 20, 2012
3:15 PM - 3:45 PM
Room:   Hall C2.2
CCH - Congress Center Hamburg
Speakers:   Ulrich Brüning, University of Heidelberg
Abstract:   High performance computing requires optimized interconnects in order to serve the increasing computing power from multi and many core CPUs.
In order to design scalable HPC systems the principles of performance improvements should be applied to the interconnect to increase the bandwidth and to reduce the latency. A careful analysis of latency components and pipeline structure must be done to answer the question "where are the limits and where can we gain what?"
The physical limits of the electrical interfaces will be analyzed and the path to ultra low latency will be presented.
  • Tutorial Pass
  • HPC in Asia Workshop Pass
  • Conference Pass
  • Conference Pass or Exhibition Pass
    Satellite Event marked with * requires separate pass
  • Morning & Afternoon Coffee Breaks
    Midday Lunch Break
Program may be subject to changes.